1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and more particularly, to a fabrication method of a semiconductor device equipped with a layer of metal silicide such as titanium silicide, in which the so-called self-aligned silicide (SALICIDE) technique is preferably used.
2. Description of the Prior Art
In recent years, semiconductor devices have been becoming miniaturized more and more and their integration scale has been becoming higher and higher. Under such the circumstances, a lot of electronic devices such as memory or logic devices, which have been designed under the design rule as narrow as 0.15 to 0.25 .mu.m, have been integrated on a semiconductor chip. In these highly-integrated devices, Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are typically used.
To cope with the progressing miniaturization and increasing integration tendency, there has been the strong need to decrease the length of gate electrodes and the width of source/drain regions for the MOSFETs. However, the decrease of the length of gate electrodes and the width of source/drain regions increase their electric resistance, thereby delaying the operation speed of the devices.
Accordingly, in the electronic devices thus miniaturized and integrated, it has been popular that silicide layers are additionally formed in the surface regions of the gate electrodes and the source/drain regions to thereby lower their electric resistance. The silicide layers for the MOSFETs are typically formed with the use of the so-called "SALICIDE" technique.
A first example of the conventional fabrication methods of this sort is shown in FIGS. 1A to 1E.
It is needless to say that a lot of MOSFETs are formed and integrated on a semiconductor substrate. However, only one of the MOSFETs is explained in this specification and attached drawings for the sake of simplification.
First, as shown in FIG. 1A, an isolation oxide 1102 is selectively formed on the surface region of a single-crystal silicon (Si) substrate 1101 by a Local Oxidation of Silicon (LOCOS) process, thereby defining a device region 1101A in which a MOSFET is formed. An impurity is selectively ion-implanted into the substrate 1101 to form channel stop regions, thereby raising the dielectric breakdown voltage. A silicon dioxide (SiO.sub.2) film 1103 is formed on the whole exposed surface of the substrate 1101 in the device region 1101A by a thermal oxidation process.
Then, a polysilicon film (not shown) with a thickness of approximately 150 nm is deposited on the SiO.sub.2 film 1103 over the whole substrate 1101 by a Chemical Vapor Deposition (CVD) process. The polysilicon film thus formed is doped with an impurity such as phosphorus (P) to lower its electric resistance. The polysilicon film having the lowered electric resistance is then patterned to a specific plan shape, thereby forming a gate electrode 1104 on the SiO.sub.2 film 1103 in the device region 1101A.
A SiO.sub.2 film (not shown) is deposited over the whole substrate 1101 by a CVD process to cover the polysilicon gate electrode 1104, the SiO.sub.2 film 1103, and the isolation oxide 1102 made of SiO.sub.2. Then, the SiO.sub.2 film thus deposited, the SiO.sub.2 film 1103, and the isolation oxide 1102 are etched by an anisotropic etching process, thereby forming a pair of sidewall spacers 1105 at each side of the gate electrode 1104. The sidewall spacers 1105 are made of SiO.sub.2. During this etching process, the surface of the substrate 1101 is uncovered at the locations for source/drain regions. The remaining SiO.sub.2 film 1103 serves as a gate oxide film. The gate electrode 1104 is located on the gate oxide film 1103 thus formed.
Subsequently, an impurity such as arsenic (As) or boron (B) is selectively implanted into the device region 1101A of the substrate 1101 by an ion-implantation process. The substrate 1101 is then subjected to a heat treatment at a temperature of 800 to 1000.degree. C., thereby forming a pair of source/drain regions 1106 at each side of the gate electrode 1104 in the device region 1101A. The pair of source/drain regions 1106 are formed in self alignment to the gate electrode 104 and the pair of sidewall spacers 1105. The state at this stage is shown in FIG. 1A.
Following this step, a titanium (Ti) film 1107 with a thickness of approximately 50 nm is deposited over the whole substrate 1101 by a sputtering process, as shown in FIG. 1B. The substrate 1101 on which the Ti film 1107 has been deposited is then subjected to a first heat-treatment process in a nitrogen (N.sub.2) atmosphere kept at the atmospheric pressure at a temperature of 600 to 650.degree. C. for 30 to 60 seconds using a lamp annealing apparatus.
Thus, as shown in FIG. 1C, silicidation reaction occurs near the interfaces of the Ti film 1107 with the single-crystal silicon source/drain regions 1106 and the polysilicon gate electrode 1104, thereby forming titanium silicide (TiSi.sub.2) layers 1109, where x is approximately equal to 2. These TiSi.sub.2 layers 1109 are in the C-49 phase having a comparatively high electric resistivity of approximately 60 .mu..OMEGA..multidot.cm. At the same time as this silicidation reaction, the Ti film 1107 is nitrided to form a titanium nitride (Ti.sub.x N) film 1107' due to diffusion of the nitrogen atoms contained in the atmosphere into the Ti film 1107, where x is equal to or greater than unity (i.e., x.gtoreq.1).
Subsequently, using a mixture of water solutions of ammonia (NH.sub.3) and hydrogen peroxide (H.sub.2 O.sub.2) as an etchant, the unreacted Ti.sub.x N film 1107' is removed by a wet etching process. As a consequence, the TiSi.sub.2 layers 1109 are left on the surface regions of the pair of source/drain regions 1106 and the gate electrode 1104, respectively, as shown in FIG. 1D.
Moreover, the substrate 1101 having the TiSi.sub.2 layers 1109 is subjected to a second heat-treatment process in a nitrogen (N.sub.2) atmosphere kept at the atmospheric pressure at a temperature of approximately 850.degree. C. for approximately 60 seconds using a lamp annealing apparatus. Thus, the TiSi.sub.2 layers 1109 with the C-49 phase are transformed to TiSi.sub.2 layers 1111 with the C54-phase having a comparatively low electric resistivity of approximately 20 .mu..OMEGA..multidot.cm, as shown in FIG. 1E.
The reason why the above-described first heat-treatment process to form the TiS.sub.x film 1109 with the C-49 phase is carried out in a N.sub.2 atmosphere is as follows.
Specifically, in the above-described silicidation reaction of Ti with Si, Si serves as a diffusion species. Therefore, Si atoms are introduced into not only the gate electrode 1104 and the source/drain regions 1106 but also the isolation oxide 1102 due to diffusion during this silicidation reaction process. If these Si atoms diffused into the isolation oxide 1102 react with Ti, a TiSi.sub.2 layer is formed on the isolation oxide 1102, thereby degrading the electrical isolation performance of the isolation oxide 1102. The phenomenon that the undesired TiSi.sub.2 layer is formed on the isolation oxide 1102 has been termed the "overgrowth". To avoid this "overgrowth" phenomenon, the first heat-treatment process is performed in a N.sub.2 atmosphere to cause a reaction of Ti with N, thereby forming the Ti.sub.x N film 1107'.
Since the reaction temperature of Ti.sub.x N is lower than that of TiSi.sub.2, the whole Ti film 107 on the isolation oxide 1102 is consumed by the formation reaction of Ti.sub.x N during the silicidation reaction. This means that the Ti film on the isolation oxide 1102 does not react with Si and consequently, TiSi.sub.2 is prevented from being formed on the isolation oxide 1102. This makes it possible to form the C-49-phase TiSi.sub.2 films 1109 on the pair of source/drain regions 1106 and the gate electrode 1104 in self alignment to the gate electrode 1104, the pair of sidewall spacers 1105, and the isolation oxide 1102 as desired.
A second example of the conventional fabrication methods of this sort, in which the "overgrowth" phenomenon is avoided, is shown in FIGS. 2A to 2F. This example is disclosed in the Japanese Patent Application No. 7-303928 that corresponds to the Japanese Non-Examined Patent Publication Nos. 9-186104 and 9-186105 published in July 1997.
First, as shown in FIG. 2A, in the same way as that of the first example shown in FIGS. 1A to 1E, the isolation oxide 1102 is formed on the surface region of the single-crystal silicon substrate 1101 to define the device region 1101A. The polysilicon gate electrode 1104 is formed on the surface of the substrate 1101 through the gate oxide film 1103. The pair of sidewall spacers 1105 are formed on the surface of the substrate 1101 at each side of the gate electrode 1104. The pair of source/drain regions 1106 are formed in the device region 1101A at each side of the gate electrode 1104. The state at this state is shown in FIG. 2A.
Subsequently, a Ti film 1107 with a thickness of approximately 20 nm is deposited over the whole substrate 1101 by a sputtering process, as shown in FIG. 2B. Then, a Ti.sub.x N film 1108 with a thickness of approximately 50 nm is deposited on the Ti film 1107 thus deposited over the whole Ti Film 1107 by a sputtering process, as shown in FIG. 2C.
Following this step, the substrate 1101 on which the Ti and Ti.sub.x N films 1107 and 1108 have been deposited is subjected to a first heat-treatment process in an argon (Ar) atmosphere kept at the atmospheric pressure at a temperature of 700.degree. C. for 30 seconds using a lamp annealing apparatus. Thus, silicidation reaction occurs near the interfaces of the Ti film 1107 with the pair of source/drain regions 1106 and the gate electrode 1104, thereby forming TiSi.sub.2 layers 1109, as shown in FIG. 2D. These TiSi.sub.2 layers 1109 are in the C-49 phase having a comparatively high electric resistivity.
At the same time as this silicidation reaction, the nitrogen atoms existing in the overlying Ti.sub.x N film 1108 are diffused into the Ti film 1107, thereby transforming the Ti film 1107 to a Ti.sub.x N film 1107' due to nitridation reaction.
Subsequently, using a mixture of water solutions of NH.sub.3 and H.sub.2 O.sub.2 as an etchant, the whole Ti.sub.x N film 1108 and the unreacted Ti.sub.x N film 1107' are removed by a wet etching process. As a consequence, the TiSi.sub.2 layers 1109 with the C-49 phase are left on the surface regions of the source/drain regions 1106 and the gate electrode 1104, as shown in FIG. 2E.
Moreover, the substrate 1101 on which the C-49-phase TiSi.sub.2 layers 1109 have been formed is subjected to a second heat-treatment process in an Ar atmosphere kept at the atmospheric pressure at a temperature of approximately 800.degree. C. for 10 seconds using a lamp annealing apparatus. Thus, the TiSi.sub.2 layers 1109 with the C-49 phase are transformed to TiSi.sub.2 layers 1111 with the C54-phase having a comparatively low electric resistivity, as shown in FIG. 2F.
The first example of the conventional fabrication methods shown in FIGS. 1A to 1E is effective for forming the C54-phase TiSi.sub.2 layers 1111 in self-alignment. However, there arises a problem that these TiSi.sub.2 layers 1111 are not formed as desired when the thickness of the layers 1111 are decreased to approximately 30 nm or less.
Specifically, the Ti film 1107 needs to become thinner according to the progressing miniaturization of semiconductor devices. However, the nitridation and silicidation reactions occurring in the Ti film 1107 tend to compete during the first heat-treatment process. Especially, when arsenic (As) is doped into the source/drain regions 1106 and the gate electrode 1104, the rate of the silicidation reaction tends to decrease and at the same time, the rate of the nitridation reaction tends to increase. As a result, the thickness of the TiSi.sub.2 layers 1109 becomes extremely small. In rare cases, only the nitridation reaction occurs in the Ti film 1107 and consequently, no TiSi.sub.2 layer is formed.
Also, since the TiSi.sub.2 layers 1109 are formed in a N.sub.2 atmosphere in the first heat-treatment process, the effects applied to the phase transition of the TiSi.sub.2 layers 1109 needs to be considered as explained below.
FIG. 3 shows the change of the phase transition temperature of the Ti film 1107 from the C-49 phase to the C54 phase with respect to the thickness of the Ti film 1107. As seen from FIG. 3, when the thickness of the Ti film 1107 is approximately 30 nm or less, the phase transition temperature rises abruptly, which is caused by the fact that the concentration of N existing in the Ti film 1107 increases due to the nitridation reaction. Therefore, the temperature of the second heat-treatment for lowering the electric resistance of the C-49-phase TiSi.sub.2 layers 1109 needs to be set higher. The higher temperature of the second heat-treatment affects badly the source/drain regions 1106 to thereby degrade the performance of the semiconductor device (i.e., the MOSFET). Also, this higher temperature decreases the temperature margin with respect to the agglomeration reaction of TiSi.sub.2.
On the other hand, the second example of the conventional fabrication methods shown in FIGS. 2A to 2F is effective for activating the silicidation reaction while suppressing the diffusion of N. Thus, the above-described problems in the first example are solved.
Specifically, in the second example, as explained above, the first heat-treatment is performed in an Ar atmosphere. Therefore, the N atoms diffuse from the Ti.sub.x N film 1108 (rather than the atmosphere) into the Ti film 1107 and as a consequence, the concentration of N in the Ti.sub.x N film 1108 becomes lower. Also, the diffusion depth of the N atoms into the Ti film 1107 becomes shallower than the case where the first heat-treatment is carried out in an N.sub.2 atmosphere as shown in the first example of FIGS. 1A to 1E. In other words, the diffusion behavior of the N atoms is suppressed effectively.
Due to this suppression of the diffusion of N into the Ti film 1107, the nitridation reaction of Ti is suppressed on the lower side of the Ti film 1107 which is contacted with the source/drain regions 1106. Accordingly, even if the thickness of the Ti film 1107 is decreased to approximately 30 nm or less, desired silicidation reaction will occur on the lower side of the Ti film 1107, realizing formation of the silicide layers 1109 with a desired small thickness.
With the second example of the conventional fabrication methods shown in FIGS. 2A to 2F, however, there is the following problem because the Ti.sub.x N film 1108 is deposited on the Ti film 1107.
Specifically, since the first heat-treatment process is carried out after the formation of the Ti.sub.x N film 1108, the Ti.sub.x N film 1108 tends to be sintered during this heat-treatment process. As a result, the Ti.sub.x N film 1108 tends to have a high stress and a high density. In this case, although the Ti film 1107 is removed by the wet etching process using the mixture of water solutions of NH.sub.3 and H.sub.2 O.sub.2, the sintered Ti.sub.x N film 1108 is difficult to be removed in the same etching process.
To cope with this difficulty in etching, the Ti.sub.x N film 1108 may be overetched so as to be removed entirely in the above wet etching process, or it may be etched entirely by an extra dry etching process after the wet etching process. In these two cases, however, there arises a problem that the underlying TiSi.sub.2 layers 1109 tend to be etched during the additional overetching or dry-etching process because the etch selectivity between TiSi.sub.2 and Ti.sub.x N is low.
Accordingly, the sheet resistance of the resultant TiSi.sub.2 layers 1111 with the C-54 phase tend to fluctuate widely and at the same time, the purpose of decreasing the electric resistance of the TiSi.sub.2 layers 1111 becomes difficult to be accomplished.
Moreover, if a Ti film is formed on a Si region surrounded by a dielectric, a TiSi.sub.2 layer is formed near the interface between the Ti film and the Si region due to silicidation reaction. In this case, the TiSi.sub.2 layer thus formed tends to sink into the Si region from its original level according to the progress of the silicidation reaction. This sinking phenomenon is caused by diffusion of the Si atoms existing in the Si region into the Ti film. Due to the sinking behavior of the TiSi.sub.2 layer during the silicidation reaction, the Ti film itself is plastically deformed.
If a Ti.sub.x N film is located on the Ti film, a plastic deformation will occur in the Ti.sub.x N film and the deformation of the Ti.sub.x N film will increase according to the progressing sinking phenomenon of the TiSi.sub.2 layer.
If the Si region has an elongated shape with a small width such as 0.5 .mu.m or smaller (i.e., a strip-like shape), the span of the Si region supported by the surrounding dielectric is short. Accordingly, the Si region becomes difficult to be plastically deformed.
The Ti.sub.x N film located on the elongated Si region make it more difficult for the Si region to be plastically deformed by the value of the stress of the Ti.sub.x N film. Thus, the rate of the silicidation reaction becomes lower than the case where the Si region does not have an elongated shape. This means that the nitridation reaction, which competes with the silicidation reaction, becomes superior. Consequently, a desired TiSi.sub.2 layer becomes difficult to be formed or no TiSi.sub.2 layer is formed.
As explained above, although the second example of the method shown in FIGS. 2A to 2F is able to cope with simple thinning of the TiSi.sub.2 layer, it is not applicable to silicidation of the thin and elongated Si region.